1. Field of the Invention
The present invention relates to a multi-rate filter bank.
2. Description of Related Art
FIG. 1 is a diagram of a conventional multi-rate filter bank 100. Referring to FIG. 1, the conventional multi-rate filter bank 100 includes a multiplexer 110, decimators 120˜150, and an anti-aliasing filter 180. The decimators 120, 130, 140, and 150 are sequentially connected with each other in series. The first decimator 120 receives an original signal DATA and decimates the same to generate a processed signal, and the decimator 130 connected after the decimator 120 receives the processed signal from the decimator 120. Similarly, the decimators 140 and 150 respectively receive processed signals from their previous decimators 130 and 140.
The multiplexer 110 receives the original signal DATA and the signals respectively generated by the decimators 120˜150. The multiplexer 110 further receives a select signal DecfSEL and outputs the original signal DATA or one of the signals generated by the decimators 120˜150 to the anti-aliasing filter 180 according to the select signal Decf SEL. The anti-aliasing filter 180 performs anti-aliasing filtering on the received signal and generates an anti-aliasing filter output signal AAFOUT.
In the conventional multi-rate filter bank 100, the multiplexer 110 only outputs one of the input signals to the anti-aliasing filter 180 at a single time point. Namely, not all the decimators 120˜150 work at a single time point. For example, none of the decimators 120˜150 works when the multiplexer 110 outputs the original signal DATA, and none of the decimators 130˜150 works when the multiplexer 110 outputs the signal generated by the decimator 120. It can be understood from foregoing description that when a decimator does not work, the internal circuit (for example, a plurality of multipliers) thereof is idled. As a result, the performance of the entire multi-rate filter bank is lowered.